ISO/IEC INTERNATIONAL STANDARD 14576 First edition 1999-12 Information technology - Synchronous split transfer type system bus (STbus) - Logical layer Technologies de I'information - Bus de systeme de transfert de fente synchrone (sTbus)- Couche logique IEC so Reference number ISO/IEC 14576:1999(E) Copyright International Organization for Standardization ted without license from IHS Not for Resale maaaiandardizato orneworkingmitedwithout licene fromH Not for Resale ISO/IEC INTERNATIONAL STANDARD 14576 First edition 1999-12 Information technology Synchronous split transfer type system bus (STbus) - Logical layer Technologies de I'information - Bus de systeme de transfert de fente synchrone (sTbus)- Couche logique @ISO/IEC1999 All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from the publisher ISO/IEC Copyright Office:Case postale 56·CH-1211Geneve 20·Switzerland IEC PRICE CODE X For price, see current catalogue Copyright International Organization for Standardization ted without license from IHS Not for Resale - i - 14576 @ ISO/IEC:1999(E) Contents Overview 1.1 Scope 1.2 Applicability 2. Definitions 2.1 Explanation of Terms 3 2.2 Notation 3. Interface Specifications .6 3.1Interface Signals 6 4. Bus Operations 11 4.1 Protocol for Basic Operations 11 4.2Transfer Protocol .16 4.2.1 Bus operation types 16 4.2.2 Command format . 16 4.2.3 Transfer sequence .25 4.3 Arbitration 27 4.4 Status Reports 27 4.5 Data Transfer .29 4.5.1 Memory access (write) .29 4.5.2 Memory access (read) .35 4.5.3 Control space access (write) .38 Control space access (read) .40 4.5.5 Message transfer ... 4.5.6 Control register access (write) 44 4.5.7 Control register access (read) ... .. 46 4.6Lock Operations 4.7Cache-related Operations 4.7.1 Cache invalidation .50 4.7.2 Retry indication ... .. 53 4.7.3 Copyback and steal operations after retry indication .. 55 4.7.4 Steal inhibit operation .. 57 4.8Error Handling 59 4.8.1 Handling errors notified in answer .. 59 4.8.2 Other error detection 61 Copyright International Organization for Standardization se from IH: Not for Resale 14576 @ ISO/IEC:1999(E) - ii - Cache Coherency Control 62 5.1Cache Control Methods 62 5.2 Cache Block Attributes .62 5.3Operations on System Bus . . 63 5.4Retry Indication .. 65 5.5Steal Operation . 66 5.6 Cache Data Management and State Transition .. 67 5.6.1 Write-through cache .67 5.6.2 Copyback cache .70 5.7 Notes on Memory Access . ..75 6.Functions for Enhanced Reliability .. .76 6.1 Redundancy . 76 6.2Detecting Faults .77 6.3Preventing Faults from Spreading ..77 6.4 Supporting Fault Handling and Diagnosis 78 Annex A (informative)Performance (Estimated) . 79 Annex B (informative)Return of answer in a lock transfer. ..80 Annex C (informative) Lock transfer and write back of copyback cache .81 Copyright International Organization for Standardization 14576 @ ISO/IEC:1999(E) - ii - Cache Coherency Control 62 5.1Cache Control Methods 62 5.2 Cache Block Attributes .62 5.3Operations on System Bus . . 63 5.4Retry Indication .. 65 5.5Steal Operation . 66 5.6 Cache Data Management and State Transition .. 67 5.6.1 Write-through cache .67 5.6.2 Copyback cache .70 5.7 Notes on Memory Access . ..75 6.Functions for Enhanced Reliability .. .76 6.1 Redundancy . 76 6.2Detecting Faults .77 6.3Preventing Faults from Spreading ..77 6.4 Supporting Fault Handling and Diagnosis 78 Annex A (informative)Performance (Estimated) . 79 Annex B (informative)Return of answer in a lock transfer. ..80 Annex C (informative) Lock transfer and write back of copyback cache .81 Copyright International Organization for Standardization 14576 @ ISO/IEC:1999(E) - ii - Cache Coherency Control 62 5.1Cache Control Methods 62 5.2 Cache Block Attributes .62 5.3Operations on System Bus . . 63 5.4Retry Indication .. 65 5.5Steal Operation . 66