ISO/IEC INTERNATIONAL STANDARD 14575 IEEE Std 1355 First edition 2000-07 Information Technology - Microprocessor Systems - Heterogeneous InterConnect (HIC) (Low-Cost, Low-Latency Scalable Serial Interconnect for Parallel System Construction) IEC Reference number so ISO/IEC 14575:2000(E) IEEEStd1355,1998Edition Copyright International Organization for Standardization itted without license from IHS Not for Resale Abstract: Enabling the construction of high-performance, scalable, modular, parallel systems with low system integration cost is discussed. Complementary use of physical connectors and cables， electrical properties, and logical protocols for point-to-point serial scalable technologies,isdescribed. Keywords: flow control, encoding schemes, OMl/HIC, packet routing, parallelism, point-to- point serial scalable interconnect, protocols, routing fabric, serial links, serialization, silicon integration, switch chip, transaction layer, wormhole routing. TheInstituteof Electrical andElectronicsEngineers,Inc 345 East 47th Street, New York, NY 10017-2394, USA Copyright @ 1998 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. First published in 1998. ISBN2-8318-5321-4 the prior written permission of the publisher. CoyrghtIntemationalOrganizationforStandardization r networking permitted without license from IHS Not for Resale ISO/IEC INTERNATIONAL STANDARD 14575 IEEE Std 1355 First edition 2000-07 Information Technology - Microprocessor Systems - Heterogeneous InterConnect (HIC) (Low-Cost, Low-Latency Scalable Serial Interconnect for Parallel System Construction) Sponsor Bus Architecture Standards Committee of theIEEEComputerSociety PRICE CODE XC IEC For price, see current catalogue Copyright International Organization for Standardization itted without license from IHS Not for Resale ISO/IEC 14575:2000(E) 2- IEEEStd1355,1998Edition CONTENTS Page FOREWORD 8 INTRODUCTION Clause 1 Scope and object . .15 2 Normative references 15 3 Definitions .. 17 3.1 General... .17 3.2 Glossary . Physical media and logical layers .23 4.1 Physical media. .23 4.2 Logical layers. .24 4.3 Interaction of layers. .27 4.4 Implementations defined in this International Standard 29 5 DS-SE and DS-DE .31 5.1 General.. ..31 5.2 DS-SE: physical medium... .32 5.3 DS-SE signal level .. .32 5.4 DS-DE: physical medium..... .38 5.5 DS-DE signal level ... .44 5.6 DS-SE and DS-DE character level... .46 5.7 DS-SE and DS-DE exchange level .48 6 TS-FO-02 fiber optic link . 6.1 Physical medium. 51 6.2 Signal level ... 53 6.3 TS-FO character level..... 55 6.4 TS-FO exchange level...... 1 HS-SE-10.... .62 7.1 HS-SE physical medium .. .62 7.2 HS-SE signal level .66 7.3 HS character level (8B/12B code) 7.4 HS exchange level. .86 8 HS-FO-10 fiber optic link .94 8.1 Physical medium .94 8.2 Signal level .. 8.3 Character level and exchange level 9 Common packet level.. .99 9.1 General discussion... .99 9.2 Packet format ..... 9.3 Networks and routing .... 9.4 Error detection, recovery, and reporting. 101 10 Conformance criteria... 101 10.1 Conformance statements 101 10.2 Definition of subsets.. .101 Copvriaht @.1998 IEEE. All rights reserved. n for Standardization e from IHS Not for Resale ISO/IEC 14575:2000(E) - 3 - IEEEStd1355,1998Edition Annex A (normative) Ds-DE connector specification . 103 Annex B (normative) HS-SE connector specification .110 Annex C (normative) TS-FO and HS-FO connector specifications 116 Annex D (informative) Rationale . 128 Annex E (informative) Switch chips, switches, and fabrics... .132 Annex F (informative) Use of the transaction layer - Asynchronous transfer mode (ATM) example.... 134 Annex G (informative) Error handling. 145 Annex H (informative) Flow control calculations , 146 Annex I (informative) Synchronized channel communications .. .149 Annex J (informative) Example DS-SE driver circuit . ..152 154 Annex L (informative) DS-DE fixed connector PCB recommendation . ..155 Annex M (informative) DS-DE cable (10 core