ISO/IEC INTERNATIONAL STANDARD 13961 IEEE Std 1596 First edition 2000-07 Information technology - Scalable Coherent Interface (SCl) IEC Reference number ISO/IEC 13961:2000(E) IEEEStd1596,1998Edition instead of a bus, uses a collection of fast point-to-point unidirectional links to provide the far higher throughput needed for high-performance multiprocessorsystems. SCl supports message-passing for loosely coupled systems. Initial SCl links are defined at 1 Gbyte/s (16-bit transactions are defined and their formal specification is provided in the form of computer programs. In addition to the usual read-and-write transactions, scl supports efficient multiprocessor lock transactions. The distributed cache-coherence protocols are efficient and can recover from an arbitrary number of transmission failures. SC protocols ensure forward progress despite multiprocessor conflicts (no deadlocks or starvation). Keywords: bus architecture, bus standard, cache coherence, distributed memory, fiber optic, interconnect,I/O system,link, mesh,multiprocessor, network, packet protocol, ring, seamless distributed computer, shared memory, switch, transaction set. The Institute of Electrical and Electronics Engineers, Inc. 345East47thStreet,NewYork,NY10017-2394,USA Copyright @ 1998 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. First published in 1998. ISBN 2-8318-5375-3 No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the prior written permission of the publisher. ISO/IEC INTERNATIONAL STANDARD 13961 IEEE Std 1596 First edition 2000-07 Information technology - Scalable Coherent Interface (SCl) Sponsor Microprocessorand MicrocomputerStandards Subcommittee oftheIEEEComputerSociety IEC PRICE CODE XF Forprice, seecurrentcatalogue ISO/IEC13961:2000(E) 2 IEEEStd1596,1998Edition CONTENTS Page FOREWORD 12 Clause Introduction. 1.1 Document structure.... 1.2 SCl overview. 20 1.2.1 Scope and directions... 1.2.2 The SCI approach. .21 1.2.3 System configurations.. 1.2.4 Initial physical models ... .23 1.2.5 SCl node model .. 24 1.2.6 Architectural parameters .. 25 1.2.7 A common CSR architecture 25 1.2.8 Structure of the specification.... 1.3 Interconnect topologies.. 1.3.1 Bridged systems .. .26 1.3.2 Scalable systems . 27 1.3.3 Interconnected systems. 27 1.3.4 Backplane rings 27 1.3.5 Interconnected rings 28 1.3.6 Rectangular grid interconnects 29 1.3.7 Butterfly switches.... 1.3.8 Vendor-dependent switches .31 1.4 Transactions .31 1.4.1 Packet formats. .32 1.4.2 Input and output queues .33 1.4.3 Request and response queues .34 1.4.4 Switch queues. ..36 1.4.5 Subactions..... 1.4.6 Remote transactions (through agents). 1.4.7 Move transactions. .41 1.4.8 Broadcast moves . 1.4.9 Broadcast passing by agents .. .43 1.4.10 Transaction types.. .44 1.4.11 Message passing .45 1.4.12 Global clocks .45 1.4.13 Allocation protocols... 1.4.14 Queue allocation. 47 1.5 Cache coherence. 1.5.1 Interconnect constraints 49 1.5.2 Distributed directories . 49 1.5.3 Standard optimizations... 50 1.5.4 Future extensions ... 50 1.5.5 TLB purges . Copyright @ 1998 IEEE. All rights reserved. ISO/IEC13961:2000(E) - 3 - IEEEStd1596,1998Edition Clause Page 1.6 Reliability, availability, and support (RAS). .54 1.6.1 RAS overview ... 54 1.6.2 Autoconfiguration... .54 1.6.3 Control and status registers . 1.6.4 Transmission-error detection andisolation.. 1.6.5 Error containment .... 1.6.6 Hardware fault retry (ringlet-local, physical layer option) .. 56 1.6.7 Software fault recovery (end-to-end).... ..56 1.6.8 System debugging ... .57 1.6.9 Alternate routing ..... .57 1.6.10 Online replacement. .57 2 References, glossary, and notation.. 2.1 Normative references.. .58 2.2 Conformance levels ... .58 2.3 Terms and definitions 2.4 Bit and byte ordering.... ..66 2.5 Numerical values ... 2.6 C code. .68 3 Logical protocols and formats .68 3.1 Packet formats.. 3.1.1 Packet types 3.2 Send and echo pack